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TPS65120
SLVS531 - JUNE 2004
SINGLE-INDUCTOR QUADRUPLE-OUTPUT TFT LCD POWER SUPPLY
FEATURES
* Main Output, VMAIN - Adjustable Voltage, 3.0 V to 5.6 V/25 mA - Post-Regulated for Low Ripple (5mVPP) - 0.8% Typical Accuracy - Efficiency up to 83% Positive Output, VGH - Adjustable Voltage up to 20 V/2 mA - 3% Typical Accuracy Negative Output, VGL - Adjustable Voltage down to -18 V/2 mA - 3% Typical Accuracy Auxiliary 1.8 V/3.3 V Linear Regulator * * * * * * * * * * * * * Automatic or Programmable Power Sequencing Complete 1 mm Component Profile Solution 2.5 V to 5.5 V Input Voltage Range Output Short Circuit Protected 16-Pin QFN Package (3 x 3 x 0,9 mm)
*
APPLICATIONS
Small Form Factor a-Si and LTPS TFT LCD Cell Phones, Smart Phones PDAs, Pocket PCs Portable DVD Digital-Still Cameras, Camcorders Handheld Instruments Portable GPS Car Navigation Systems
*
*
DESCRIPTION
The TPS6512x DC-DC converter supplies all three voltages required by amorphous-silicon (a-Si) and low-temperature poly-silicon (LTPS) TFT-LCD displays. The compact layout of the TPS6512x uses a single inductor to generate independently-regulated positive and negative outputs. A free-running variable peak current PWM control scheme time-multiplexes the inductor between outputs. This control architecture operates at a pseudo-fixed-frequency to provide fast response to line and load transients while maintaining a relatively constant switching frequency and high efficiency over a wide range of input and output voltages. Due to the high switching frequency capability of the device, inexpensive and ultra-thin 8.2 or 10 H inductors can be used. The main output, VMAIN, is post-regulated to provide a low-ripple source drive voltage for the LCD display. The auxiliary outputs generate a boosted output voltage, VGH, up to 20 V, and a negative output voltage, VGL, down to -18 V for the LCD gate drive. The device has internal current limiting for high reliability under fault conditions. Additionally, the device offers a fixed output linear regulator for the LCD logic circuitry.
100
TPS65123 VIN 2.7 V to 5.5 V VIN C1 2.2 F RUN EN GATE VGH up to 20 V/2 mA C2 100 nF R1 FBH R2 VGH SWP FBL VMAIN FBM BOOT VMAIN R5 C4 R6 1 F 3.0 V to 5.3 V/25 mA C5 220 nF SWN L1 10 H D1 VGL R3 R4 down to -18 V/2 mA C3 100 nF
90 80 70 60 50 40 30 20 10 0 5.5 5.2 4.7 4.0 3.2 2.8 2.6 2.4 2.3 24.0 20.0 16.0 12.0 8.0 4.0
AGND
A
PGND
A
VIN - Input Voltage - V
IBOOT - Load Current - mA
Figure 1. Typical Application
Figure 2. Core Converter Efficiency
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2004, Texas Instruments Incorporated
Core Converter Efficiency - %
0.9
0.5
0.1
TPS65120
SLVS531 - JUNE 2004
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION
TA INTEGRATED LINEAR REGULATOR Fixed 3.3V output voltage Fixed 1.8V output voltage -40 to 85C NO NO POWER SEQUENCING Automatic Power-Up/Down Automatic Power-Up/Down Automatic Power-Up/Down Programmable Power-Up/Down PACKAGE 3 x 3 QFN-16 3 x 3 QFN-16 3 x 3 QFN-16 3 x 3 QFN-16 PART NUMBER (1) TPS65120RGT TPS65121RGT TPS65123RGT TPS65124RGT PACKAGE MARKING BKA BKB BKC BKD
(1)
The xyz package is available in tape and reel. Add R suffix (xyzR) to order quantities of TBD parts. Add T suffix (xyzT) to order quantities of 250 parts.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT VIN Input voltage (2) SWN SWP VGH Voltage (2) VMAIN, LDOIN, LDOOUT, ENVGL, ENVGH BOOT Input voltage at GATE, EN, RUN Power dissipation Operating temperature range Maximum operating junction temperature, TJ(max) Storage temperature range (1) (2)
(2)
-0.3 V to +6 V VIN - 24 V to VIN +0.3 V - 0.3 V to +23 V - 0.3 V to +21 V - 0.3 V to +6 V - 0.3 V to +6.2 V -0.3 V to VIN + 0.3 V Internally limited -40C to 85C 135C 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS (1)
PACKAGE RGT (1) RJA 68C/W DERATING FACTOR ABOVE TA = 25C 15mW/C
Maximum power dissipation is a function of TJ(max), JA and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = [TJ(max)-TA]/ JA.
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TPS65120
SLVS531 - JUNE 2004
ELECTRICAL CHARACTERISTICS
VIN = 3.6 V, EN = RUN = VIN, L = 10 H, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted)
PARAMETER CONVERTER STAGE Input voltage for full load operation VIN Minimum input voltage for start-up RL_MAIN 330 at VMAIN = 5 V, RL_VGH 12 k at VGH = 12 V, RL_VGL 12 k at VGL = -12 V, VLDOIN= GND, TA = -40C to 85C RL_MAIN 660 at VMAIN = 5 V, RL_VGH 24 k at VGH = 12 V, RL_VGL 24 k at VGL = -12 V, VLDOIN= GND, TA = -20C to 85C RL_MAIN = 250 at VMAIN = 5 V VLDOIN= ENVGH = ENVGL = GND VIN 2.7 V VIN 2.5 V VIN 2.7 V VIN 2.5 V VIN 2.5 V PTOT Total output power on VBOOT + VGH + VGL VIN 2.7 V VIN 3 V VIN 4.5 V ILIM ISTART-UP Power efficiency P-MOS1 current limit P-MOS1 start-up current limit P-MOS1 switch on-resistance rDS(ON) N-MOS1 switch on-resistance P-MOS1 leakage current N-MOS1 leakage current N-MOS2 + P-MOS2 forward voltage drop N-MOS3 + D1 forward voltage drop CONVERTER SUPPLY CURRENT Quiescent current into VIN Quiescent current into BOOT IQ Quiescent current into VGH ISD Shutdown current IMAIN = IGH = IGL = 0 mA, VGH = +15 V, VGL = -15 V, VMAIN = 5 V, VFBH = VFBM = +1.5 V, VFBL = -0.2 V, VBOOT = 5.25 V, VLDOIN = GND, EN = RUN = VIN, TA = 25C TA = 25C 140 30 0.1 0.1 170 60 A 1 1 A VMAIN = 5.0 V, IBOOT = 20 mA, VGH = 15 V, VGL = -10 V, IGH = IGL = 100 A, VLDOIN = GND 2.7 V VIN 5.5 V 2.7 V VIN 5.5 V VIN = VGS = 3.6 V VIN = VGS = 2.5 V VBOOT = VGS = 3.7 V VBOOT = VGS = 5 V VDS = 6 V VGS = VBOOT = 5.5 V, VSWP = 2 V, IBOOT = ID = 50 mA VGS = VBOOT = 5.5 V, VSWP = 2 V, IGH = ID = 50 mA 35 15 35 15 60 120 150 250 83% 150 65 2.5 3.8 1.9 1.4 0.01 0.01 400 900 4.3 6.9 3.5 2.3 1 1 600 1100 200 mA mA A mV mV mW 2.7 5.5 V TEST CONDITIONS MIN TYP MAX UNIT
2.5
V
f PGH PGL
Switching frequency Output power on VGH Output power on VGL
4.0
MHz mW mW
3
TPS65120
SLVS531 - JUNE 2004
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.6 V, EN = RUN = VIN, L = 10 H, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted)
PARAMETER MAIN OUTPUT VMAIN IMAIN Main output voltage range Maximum main output current VMAIN 5.3 V VMAIN 5.3 V 2.7 V VIN 5.5 V, 100 A IMAIN 25 mA, TA = -20C to 50C 2.7 V VIN 5.5 V, 0 mA IMAIN 25 mA VFBM= VREF IMAIN = 0 to 25 mA, VMAIN = 5 V IMAIN = 10 mA IMAIN = 10 mA VBOOT = 5.5 V 10 3.0 25 7.5 1.203 1.195 1.213 1.213 0.01 0.006 130 5 50 1.223 1.231 0.1 5.6 V mA V V A %/mA mV mVP-P mA k TEST CONDITIONS MIN TYP MAX UNIT
VFBM IFBM
Feedback regulation voltage
Feedback input bias current Load regulation Minimum dropout voltage Main output voltage ripple
ISC_MAIN RDIS_VMAIN
Short-circuit current limit Discharge resistor for power-down sequence VGH output voltage range Maximum DC output current VGH precharge resistor
VGH OUTPUT VGH IGH VFBH IFBH VIN + 0.5 1 2.7 V VIN 5.5 V, 0 mA IGH 2 mA VFBH = 0 V IGH = 0 to 2 mA, VGH = 15 V VIN = 2.7 V to 5.5 V, IGH = 100 A 200 A load, VGH = 15 V, COUT = 220 nF, CFF = 10 pF 1.177 1.213 0.01 -0.11 0.01 20 10 1.249 0.1 20 6 V mA k V A %/mA %/V mV k
Feedback regulation voltage Feedback input bias current Load regulation Line regulation VGH output voltage ripple
RDIS_VGH
Discharge resistor for power-down sequence VGL Output voltage range Maximum DC output current Feedback regulation voltage Feedback input bias current Load regulation Line regulation VGL output voltage ripple 2.7 V VIN 5.5 V, 0 mA IGL 2 mA VFBL = 0 V IGL = 0 to 2 mA, VGL = -15 V VIN = 2.7 V to 5.5 V, IGL = 100 A 200 A load, VGL = -15 V, COUT = 220 nF -0.036 -18
VGL OUTPUT VGL IGL VFBL IFBL -2.5 6 0 0.01 0.13 0.1 20 0.036 0.1 V mA V A %/mA %/V mV
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TPS65120
SLVS531 - JUNE 2004
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.6 V, EN = RUN = VIN, L = 10 H, TA = -40C to 85C, typical values are at TA = 25C (unless otherwise noted)
PARAMETER LINEAR REGULATOR STAGE - AUXILIARY OUTPUT VLDOIN VLDOOUT ILDOOUT ISC_LDO Input voltage range Output voltage range Maximum output current Short-circuit current limit Minimum dropout voltage Total accuracy Load regulation Line regulation IQ_LDO ISD_LDO Linear regulator quiescent current Linear regulator shutdown current Gate output pull-down resistance Gate output pull-up resistance VIH VIL VUVLO VIH VIL ILKG High level input voltage Low level input voltage Undervoltage lockout threshold High level input voltage Low level input voltage Logic input leakage current EN, RUN pin pull-down resistance ENVGL, ENVGH = VIN or GND (TPS65124) EN, RUN = VIN EN, RUN 0.4 v 0.01 0.01 100 VIN falling 1.4 0.4 0.1 0.1 2.15 1.4 0.4 2.3 VLDOOUT = 0 V ILDOOUT = 10 mA 2.5 V VLDOIN 5.5 V, 0 mA ILDOOUT 20 mA ILDOOUT = 0 to 20 mA VLDOIN = VLDOOUT + 0.5 V (min 2.5 V) to 5.5 V, ILDOOUT = 20 mA VLDOIN = VLDOOUT + 0.4 V (min 2.5 V), TA = 25C GATE = VIN VGATE < 500 mV 0.006 0.013 11 0.2 100 100 20 1 2.5 1.8 20 50 400 3% %/mA %/V A A k k V V V V V A k 5.8 VLDOIN -0.5 V V mA mA mV TEST CONDITIONS MIN TYP MAX UNIT
GATE DRIVER
UNDERVOLTAGE LOCKOUT LOGIC SIGNALS EN, RUN, ENVGL, ENVGH
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TPS65120
SLVS531 - JUNE 2004
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PIN ASSIGNMENTS
TPS65120/1/2 (TOP VIEW)
GATE SWN SWP VIN
TPS65123 (TOP VIEW)
GATE SWN SWP VIN
TPS65124 (TOP VIEW)
GATE SWN
14
EN RUN LDOIN LDOOUT
1 2 3 4
16
15 14
13 12
PGND BOOT VGH FBH
EN RUN AGND AGND
1 2 3 4
16
15 14
13 12
PGND BOOT VGH FBH
EN RUN ENVGL ENVGH
1 2
16
15
SWP
13 12
VIN
PGND BOOT VGH FBH
Exposed 11 Thermal Die* 10 AGND 5 6 7 8 9
Exposed 11 Thermal Die* 10 AGND 5 6 7 8 9
Exposed 11 Thermal Die* 3 10 AGND 4 5 6 7 8 9
VMAIN
VMAIN
TERMINAL FUNCTIONS
TERMINAL NAME VIN GATE RUN EN SWN SWP PGND VGH BOOT VMAIN FBH FBL FBM AGND LDOIN LDOOUT ENVGL ENVGH NO. 15 16 2 1 14 13 12 10 11 8 9 5 6 7, 3, 4 3 4 3 4 I O I I I/O I I/O I I I/O I/O O O O I I I I This is the input voltage pin of the device. This pin can either be the gate driver output to an external small P-Channel MOSFET (see application section), or an active high control input. Pulling GATE above the 1.4 V logic-high level and RUN to a logic-low level disables the integrated active power-down sequencing. RUN controls the external P-Channel MOSFET. This pin must be terminated and not be left floating. Forcing this pin to a logic-high level turns on the external MOSFET switch. This is the enable pin of the multiple-output dc-to-dc converter. This pin must be terminated and not be left floating. A simultaneous logic-high level on EN and RUN enables the converter and a logic-low shuts down the device. Connect the inductor to this pin. This pin is connected to the source of the high-side MOSFET switch. Connect the inductor to this pin. This pin is connected to the drain of the low-side MOSFET switch. Power ground. Connect to AGND underneath the IC. Positive output Provides a bootstrapped supply for the rectifier MOSFET driver, enabling the gate of the MOSFET to be driven above the output voltage. Main output Feedback pin for the positive output voltage divider. Regulates to 1.213 V nominal. Feedback pin for the negative output voltage divider. Regulates to 0 V nominal. Connect feedback resistor divider between VGL and main output. Feedback pin for the main output voltage divider. Regulates to 1.213V nominal. Analog ground. Connect to power ground (PGND) underneath IC. Pins 3 and 4 are only used for AGND in TPS65123. Auxiliary linear regulator input. If this pin is connected to GND, the voltage regulator is disabled (TPS65120/1/2). The low-dropout series-pass regulator (LDO) is enabled according to the GATE signal timing. Auxiliary linear regulator output (TPS65120/1/2). Enable pin for negative output (TPS65124). This pin should be terminated and not be left floating. Enable pin for positive output (TPS65124). This pin should be terminated and not be left floating. DESCRIPTION
6
VMAIN
AGND
AGND
AGND
FBM
FBM
FBM
FBL
FBL
FBL
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TPS65120
SLVS531 - JUNE 2004
FUNCTIONAL BLOCK DIAGRAM - TPS65120/1/2/3
GATE VIN
Power Down Seq Off 100kR
Undervoltage Lockout Bias Supply
VMAIN Oscillator RUN S EN V REF BOOT EN
Current Limit Comparator Ton
P-MOS1
Min Off Time
SWN
R SWP N-MOS3 BOOT D1 VGH
V REF FBH
R
RDIS_VGH
R FBL Control Logic Power Up/Down Sequencer
N-MOS2 BOOT
P-MOS2 BOOT FBM
VMAIN
EN
LDO
VMAIN
Power Down Seq Off
R DIS_VMAIN
V REF= 1.213V Bandgap BOOT N-MOS1 AGND
PGND
LDOIN
LDO EN_LDOAUX NOT PRESENT IN TPS65123
LDOOUT
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TPS65120
SLVS531 - JUNE 2004
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FUNCTIONAL BLOCK DIAGRAM - TPS65124
GATE VIN
Power Down Seq Off 100kR Undervoltage Lockout Bias Supply
VMAIN Oscillator RUN S EN EN
Current Limit Comparator Ton
P-MOS1
Min Off Time SWN
V REF BOOT
R
SWP
N-MOS3 BOOT V REF FBH R Control Logic
D1 VGH RDIS_VGH
R FBL
P-MOS2 N-MOS2 BOOT BOOT FBM
Power Up/Down VMAIN Sequencer EN LDO VMAIN
RDIS_VMAIN Power Down Seq Off ENVGH ENVGL BOOT
N-MOS1 AGND
Bandgap
V REF = 1.213V PGND
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TPS65120
SLVS531 - JUNE 2004
PARAMETER MEASUREMENT INFORMATION
TPS65120 V IN 2.7 V to 5.5 V VIN C1 2.2 W F RUN EN GATE V GH up to 20 V/2 mA C2 220 nF VGH R1 FBH R2 LDOIN LDOOUT AGND A List of Components: U1 = TPS6512x L1 = EPCOS SIMID1812-C D1 = ZETEX ZUMD54C CX = X5R/X7R PGND A VAUX 3.3 V/20 mA C6 220 nF SWP FBL VMAIN FBM BOOT C4 1WF SWN L1 10 W H R3 R4 D1 VGL down to -18 V/2 mA C3 220 nF
R5
V MAIN 3.0 V to 5.3 V/20 mA C5 220 nF
R6
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE Core converter efficiency Main output efficiency VMAIN Output ripple voltage DC output voltage Load transient response VGH, VGL VGH VGL fs IQ Positive, negative output ripple voltage DC output voltage DC output voltage Switching frequency No load quiescent current Power-Up Sequencing (TPS65120) Power-Down Sequencing (TPS65120) vs Load current vs Load current vs Load current vs Input voltage vs Load current vs Load current vs Input voltage vs Load current vs Input voltage 3 4 5 6 7 8 9 10, 11 12 13 14 15 16 17
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TPS65124 CORE CONVERTER EFFICIENCY vs LOAD CURRENT
100 90 Core Converter Efficiency - % 80 70 60 50 40 30 20 10 0 0.1 1 10 100 IBOOT - Output Current - mA VIN = 3.6 V ENVGL = ENVGH = GND VMAIN = 5 V Core Converter Efficiency - % 100 95 90 85 80 75 70 65 60 2.7
TPS65124 CORE CONVERTER EFFICIENCY vs INPUT VOLTAGE
VIN = 3.6 V, VMAIN = 5 V, ENVGL = ENVGH = GND IBOOT = 15 mA
IBOOT = 5 mA
3.1
3.5 3.9 4.3 4.7 VIN - Input Voltage - V
5.1
5.5
Figure 3. MAIN OUTPUT EFFICIENCY vs LOAD CURRENT
100 VIN = 3.6 V 90 Main Output Efficiency - % VMAIN = 5 V, VGH = 15 V @ 200 WA, VGL = -10 V @ 200 WA 100 95 90 Main Output Efficiency - % 85 80 75 70 65 60 55 50 45 30 0 2 4 6 8 10 12 14 16 18 20 40 2.7 3.1
Figure 4. MAIN OUTPUT EFFICIENCY vs INPUT VOLTAGE
80 70
VMAIN = 5 V @ 10 mA, VGH = 15 V @ 200 WA, VGL = -10 V @ 200 WA
60 50
VMAIN = 3.3 V, VGH = 7.5 V @ 200 WA, VGL = -3 V @ 200 WA
VMAIN = 5 V @ 5 mA, VGH = 15 V @ 200 WA, VGL = -10 V @ 200 WA VMAIN = 3.3 V @ 10 mA, VGH = 7.5 V @ 200 WA, VGL = -3 V @ 200 WA
40
IMAIN - Output Current - mA
3.5 3.9 4.3 4.7 VIN - Input Voltage - V
5.1
5.5
Figure 5.
Figure 6.
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TPS65120
SLVS531 - JUNE 2004
MAIN OUTPUT RIPPLE VOLTAGE
5.05 5.04
VBOOT (50 mV/div, 5.8 V Offset)
MAIN DC OUTPUT VOLTAGE vs LOAD CURRENT
VIN = 3.6 V, VGH = 15 V @ 200 WA, VGL = -10 V @ 200 WA
5.03 V MAIN - Output Voltage - V
VIN = 3.6 V, VMAIN = 5 V @ 20 mA, ENVGL = ENVGH = LOW t - Time - 5 Ws/div
5.02 5.01 5 4.99 4.98 4.97 4.96 4.95 0 2 4 6 8 10 12 14 16 IMAIN - Output Current - mA 18 20
VMAIN (10 mV/div, 5 V Offset)
Figure 7. MAIN OUTPUT LOAD TRANSIENT RESPONSE
VIN = 3.6 V, VMAIN = 5 V, ENVGL = ENVGH = LOW VMAIN (50 mV/div, 5 V Offset)
Figure 8.
POSITIVE, NEGATIVE OUTPUT RIPPLE
VIN = 3.6 V, VMAIN = 5 V @ 5 mA, VGH = 15 V @ 100 WA, VGL = -10 V @ 100 WA VGH (50 mV/div, AC Coupled)
IMAIN (10 mA/div) COUT = 220 nF
VGL (20 mV/div, AC Coupled)
t - Time - 20 Ws/div
t - Time - 10 Ws/div
Figure 9.
Figure 10.
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TPS65120
SLVS531 - JUNE 2004
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POSITIVE, NEGATIVE OUTPUT RIPPLE VOLTAGE
VIN = 3.6 V, VMAIN = 5 V @ 5 mA, VGH = 15 V @ 100 WA, VGL = -10 V @ 100 WA
VGH - DC Output Voltage - V
POSITIVE OUTPUT (VGH) LOAD REGULATION
15.15 VIN = 3.6 V, VMAIN = 5 V, @ 5 mA VGL = -10 V @ 200 WA
VGH (20 mV/div, AC Coupled)
10 pF Feed-Forward Capacitor Across R1
15.10
15.05
15
14.95
VGL (20 mV/div, AC Coupled)
14.90
14.85 t - Time - 10 Ws/div
0.1
1 IGH - Output Current - mA
10
Figure 11.
Figure 12. SWITCHING FREQUENCY vs LOAD CURRENT
10 VIN = 3.6 V, VMAIN = 5 V, ENVGH = ENVGL = GND Switching Frequency - MHz
NEGATIVE OUTPUT (VGL) LOAD REGULATION
-9.90 -9.92
VGL - DC Output Voltage - V
VIN = 3.6 V, VMAIN = 5 V @ 5 mA, VGH = 15 V @ 200 WA
-9.94 -9.96 -9.98 -10 -10.02 -10.04 -10.06 -10.08 -10.10 0.1 1 IGL - Output Current - mA 10
1 0.1 1 10 100 IMAIN - Output Current - mA
Figure 13.
Figure 14.
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TPS65120
SLVS531 - JUNE 2004
QUIESCENT CURRENT vs INPUT VOLTAGE
300 RUN 250 I Q - Quiescent Current - WA VLOGIC (5 V/div)
TPS65120 POWER-UP SEQUENCING
VLOGIC
200
VMAIN (2 V/div)
VMAIN
150 VGH (5 V/div)
VGH
100
50
VMAIN = 5 V, VGH = 15 V, VGL = -10 V No-Load Quiescent Current Includes Output Voltage Divider Network Bias Current 2.5 2.8 3 3.3 3.5 3.8 4 4.3 4.5 4.8 5 5.3 5.5
VGL (5 V/div)
VGL
VIN = 3.6 V, EN = HIGH, RMAIN = 1 kW, RGH = 120 kW, RGL = 100 kW,
0 t - Time - 100 s/div VIN - Input Voltage - V
Figure 15. TPS65120 POWER-DOWN SEQUENCING
RUN VLOGIC (5 V/div) VLOGIC
Figure 16.
VMAIN (2 V/div)
VMAIN
VGH (5 V/div)
VGH VGL
VIN = 3.6 V, EN = HIGH, RMAIN = 1 kW, RGH = 120 kW, RGL = 100 kW,
VGL (5 V/div)
t - Time - 5 ms/div
Figure 17.
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TPS65120
SLVS531 - JUNE 2004
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DETAILED DESCRIPTION
The standard application circuit (Figure 1) of the TPS65120 is a complete power supply for TFT LCD displays. The circuit generates four independent supplies for the source driver (VMAIN), the gate drivers (VGH, VGL) and a logic supply for the timing controller. The input voltage range is from 2.5 V to 5.5 V. The TPS65120/1/2 contains a high-performance switching regulator and two low-dropout linear regulators (LDOs). One of the LDOs generates VMAIN and the other powers the logic inside the panel. The TPS65123 includes only one linear regulator to provide the main output with low ripple voltage and can be set from 3.0 V to 5.3 V with an external resistor voltage divider. The TPS65124 integrates programmable power sequencing for highest flexibility.
OPERATION
The TPS6512x generates both positive and negative supply voltages using a single inductor. It alternates between acting as a step-up converter and an inverting converter on a cycle-by-cycle basis. All output voltages are independently regulated. A free-running, variable-peak-current PWM control scheme is used to time-multiplex the inductor between BOOT, VGH, and VGL outputs. This inherently-stable control architecture operates at a pseudo fixed frequency, providing fast response to line and load transients while maintaining a relatively constant switching frequency and high efficiency over a wide range of input and output voltages. During the first cycle of operation, internal switches N-MOS1 and P-MOS1 are turned on. SWN connects to VIN, SWP pulls to ground and the inductor current rises. Once the inductor current reaches the DC current limit (ILIM) of 150 mA (typ) the internal control logic can either turn off N-MOS1 or P-MOS1 to service the requesting output. Depending on the required output power, the converter starts another cycle or enters a pulse-skipping modulation scheme to increase efficiency under light loads. The current into the SWN pin measures the inductor current. The TPS6512x controls the inductor current to regulate BOOT, VGH, and VGL output voltages. To achieve low ripple voltage and high accuracy, the main output (VMAIN) is post-regulated by an integrated LDO. This LDO regulator regulates energy from the BOOT output down to 5.3 V (max). To achieve the highest efficiency, the BOOT voltage is regulated to minimize the dropout voltage across the LDO to approximately VMAIN + 0.5 V. In addition, the VMAIN, VGH, VGL outputs are monitored for fault conditions that last longer than the fault-timer period of 100 s (typ). The device goes into a latched shutdown state in case of a fault condition. Soft Start The TPS6512x has an internal soft-start circuit that limits the inrush current during startup. This prevents possible voltage drops of the input voltage in case the battery or a high impedance power source is connected to the input of the device. The device powers up by precharging the BOOT output capacitor to VIN. During the precharge phase, the current through the rectifying switch N-MOS2 is limited. This also limits the output current under short-circuit conditions on the BOOT output. To ensure proper startup of the device, the BOOT output must be left unloaded during the precharge phase. After the precharge phase, the converter operates with an ISTART-UP current limit of 65 mA (typ), then increases gradually to the full current limit of 150 mA (typ). Undervoltage Lockout To ensure that the input voltage is high enough for reliable operation, the TPS6512x includes an under-voltage lockout (UVLO) circuit. The UVLO threshold at the VIN pin is 2.15 V (typ) falling and 2.25 V (typ) rising. The 100 mV (typ) hysteresis prevents supply transients from causing restarts. Once the input voltage exceeds the UVLO rising threshold, the controller can enable the reference voltage and precharges BOOT. When the input voltage falls below the UVLO falling threshold, the controller turns off the reference and all the regulator outputs, and pulls GATE high with an internal 100 k resistor to turn off P1 (Figure 18).
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TPS65120
SLVS531 - JUNE 2004
DETAILED DESCRIPTION (continued)
Enable and Power Sequencing (TPS65120/1/2/3) To correctly power up most TFT panels, the gate-drive supplies must be sequenced such that the negative supply (VGL) powers up before the positive supply (VGH). The TPS65120/1/2/3 controls this sequence through an enable pin. Once RUN is high, the TPS65120/1/2/3 turns on the external P-channel MOSFET P1 (see Figure 18) by pulling GATE low. GATE is pulled down with a 100 k resistor. The DC/DC converter then starts, enabling the BOOT output. Pulling the enable pin (EN) high enables the MAIN output. When the output voltage VMAIN has reached 90% of its nominal value, the negative output enables. VGH is delayed until the negative voltage has reached 90% of its nominal value. Pulling the RUN pin low shuts down the device. Power-down sequencing starts by switching off VGH and VGL. The VGH output capacitor is actively discharged by an internal resistor while VGL is only discharged by its feedback voltage divider. The required time to discharge the output capacitor at VGL output depends on the load current. Once VFBL has reached 1.2 V (typ) the main output is turned off followed by the output voltage VLOGIC. This sequence is shown in Figure 19. When no power sequencing is required on the digital supply voltage (VLOGIC), tie EN and RUN signals together and GATE can be connected to a logic-high level to disable the power-down sequencer. Each output turns off depending upon load current and output capacitance.
P1 R9 R10 TPS65120 VIN C1 RUN EN GATE VGH R1 C2 R2 LDOIN LDOOUT AGND A PGND A FBH VGH SWP FBL VMAIN FBM BOOT C4 SWN L1 R3 C3 R4 VMAIN R5 C5 R6 VLOGIC = 3.3 V
VIN RUN GATE, EN_LDOAUX
C7
VIN = 3.3 V
D1 VGL
5.75V VBOOT VLOGIC, EN VMAIN VGL
VGH
Figure 18. Power Sequencing on Digital Supply Voltage, VLOGIC
Figure 19. TPS65120/1/2/3 Power Sequence
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DETAILED DESCRIPTION (continued)
Enable and Power Sequencing (TPS65124) The TPS65124 controls the power sequencing of VLOGIC, VMAIN, VGH and VGL with four separate enable pins. These pins must be terminated and not be left floating to prevent instability. Once RUN is pulled high and the input voltage on VIN exceeds the rising input UVLO threshold, the reference is turned on and the external P-channel MOSFET P1 (see Figure 20) is switched on by pulling GATE low. The GATE is pulled down with a 100 k resistor. The DC/DC converter then starts up, enabling the BOOT output. Pulling enable pin high (EN) powers on the MAIN output. This power sequencing must occur before the gate voltages are enabled. Conversely VGL and VGH output voltages must be turned off by pulling ENVGL and ENVGH inputs to ground before the MAIN output is switch off. To clamp the VGLoutput near zero when the MAIN output is still on, an external diode (D2) can be used. In some applications this diode may already be implemented in the display.
P1 VLOGIC = 3.3V D2 TPS65124 VIN = 3.3V C1 RUN GATE EN VGH R1 C2 R2 FBH EN VGH SWP FBL VMAIN FBM BOOT C4 VMAIN R5 C5 R6 VIN SWN L1 R4 D1 R3 C3 optional VGL
V IN RUN GATE 5.75V V BOOT V LOGIC EN VMAIN
ENVGH ENVGL
ENVGH ENVGL AGND
A
PGND
A
ENVGH
VGH ENVGL VGL
Figure 20. Power Sequencing on Digital Supply Voltage, VLOGIC
Figure 21. TPS65124 Programmable Power Sequence
Fault Protection All TPS6512x outputs are protected against a short circuit to ground. During steady-state operation, if the output VMAIN, VGH or VGL falls below its fault detection threshold the device simultaneously turns off all three outputs. Once VMAIN comes down to 700 mV typ, the GATE output is pulled to VIN, the auxiliary LDO (TPS65120/1/2) is disabled and the device enters a shutdown state. The auxiliary LDO present in TPS65120/1/2 has an integrated current foldback circuit for reliable short-circuit protection. The device can be enabled again by toggling the enable pins (RUN, EN) below 0.4 V or by cycling the input voltage below the UVLO falling threshold (2.15 V typ).
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APPLICATION INFORMATION OUTPUT POWER CAPABILITY
The first step in the design procedure is to calculate the maximum output current for each output under certain input and output voltage conditions. The TPS6512x uses time-multiplex operation to share the inductive storage element between BOOT, VGH and VGL outputs. To avoid complex calculations it is recommended to use the specified output-power data from the electrical characteristics table to determine the maximum output-power capability. The following example shows how to proceed for given requirements: * Input Voltage = 3.0 V * MAIN Output = 5.0 V @ 10 mA * VGH output = 12 V @ 500 A * VGL output = -12 V @ 300 A 1. Calculate Maximum Output Power on VGH Output
PGH = VGH x I GH
2. Calculate Maximum Output Power on VGL Output
PGL = VGL x IGL
3. Calculate Maximum Output Power on BOOT Output
PBOOT = PMAIN x LDO _ MAIN PBOOT = PMAIN x LDO _ MAIN
VMAIN x IMAIN VMAIN + 0.5 VMAIN x IMAIN VIN
2
2
for VIN < VMAIN + 0.5
for VIN > VMAIN
4. Maximum Output Power Verification The electrical characteristics table states that for VIN > 3.0 V, the maximum power on VGH and VGL outputs must be lower than 35 mW each. Furthermore, the total output power (PBOOT + PGH + PGL) must be lower than 150 mW. In our design example, PGH = 6 mW, PGL = 3.6 mW, and PBOOT = 55 mW. Since these numbers are well below the specified values, we can conclude that TPS6512x can reasonably power such a display.
SETTING THE OUTPUT VOLTAGE
The output voltages are defined as shown in Figure 22.
R5 + R6 R6 with an internal reference voltage VFBM typical = 1.213V. VMAIN = VFBM x R1+ R2 R2 with an internal reference voltage VFBH typical = 1.213V. VGH = VFBH x VGL = VMAIN x R3 R4
To minimize the operating quiescent current, set R2, R4 and R6 in the range 100 k to 300 k. Great care should be taken to route the FBx lines away from noise sources such as the inductor or the SWN and SWP lines. A feed-forward capacitor across the upper feedback resistor (R1, R3) on VGH and VGL outputs can be used to provide more overdrive for the error comparator. This feed-forward capacitor helps to reduce the output ripple voltage. A good starting value is 10 pF.
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APPLICATION INFORMATION (continued)
The larger the feed-forward capacitor the worse the load regulation of the device. Therefore, when concern for load regulation is paramount, select a capacitor value as small as possible. Another possibility to further reduce ripple voltage on VGH and VGL outputs is to increase output-capacitor values (C2, C3).
VIN 2.7 V to 5.5 V C1 2.2 F VGH up to 20 V/2 mA R1 C2 100 nF FBH R2 LDOIN LDOOUT AGND A PGND A C6 220 nF VAUX 3.3 V/20 mA TPS65120 VIN RUN EN GATE VGH SWP FBL VMAIN FBM BOOT SWN L1 10 H R3 R4 D1 VGL down to -18 V/2 mA C3 100 nF VMAIN 3.0 V to 5.3 V/25 mA C5 220 nF
R5 C4 1 F R6
Figure 22. Typical Application
INDUCTOR SELECTION
Since the control scheme of the TPS6512x device is inherently stable, the inductor value does not affect the stability of the converter. To operate the TPS6512x properly at full performance, choose inductors in the range 8.2 H to 10 H. The selection of the inductor is primarily based on the required output power. The variable peak current PWM control scheme used in TPS6512x automatically adapts the peak inductor current (between 65mA typ. and 150mA typ.) depending on output power and input voltage. At moderate loads, the converter typically operates with a peak inductor current in the range of 65mA to 100mA, allowing the use of inductors in the 0603 case size. In order not to saturate the inductor when operating at a higher output power, select an inductor with a higher saturation-current rating. The inductor series in Table 1 from various suppliers have been used with the TPS6512x converter. Table 1. List of Inductors
MANUFACTURER TAIYO YUDEN SERIES LQ LB1608 LQ CB2012 LQ CBL2012 TDK GLF1608 GLF2012 DIMENSIONS 1.6 x 0.8 x 0.8 = 1.02 mm3 2.0 x 1.2 x 1.2 = 2.88 mm3 2.0 x 1.2 x 1.0 = 2.40 mm3 1.6 x 0.8 x 0.8 = 1.02 mm3 2.0 x 1.2 x 1.2 = 2.88 mm3
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DIODE SELECTION
To achieve high efficiency, use a Schottky diode. The voltage rating must be higher than the input voltage plus the absolute value of the negative output. The current rating of the diode must meet the converter peak inductor-current rating when servicing the VGL output. The main parameter affecting the efficiency of the converter is the forward voltage and the reverse leakage current of the diode, both should be as low as possible. The following diodes from different suppliers listed in Table 2 have been used with the TPS6512x converter. Table 2. List of Diodes
MANUFACTURER ROHM VISHAY ZETEX REFERENCE RB521G-30 BAT54-HT3 ZUMD54 REVERSE VOLTAGE 30 V 30 V 30 V
CAPACITOR SELECTION
The TPS65120 converter requires six capacitors. The input capacitor is primarily a function of the board layout. In designs with long traces, for good input filtering, we recommend a ceramic input capacitor (X5R/X7R type) of at least 1 F placed as close as possible to the converter. To operate properly, the TPS6512x requires a bootstrap capacitor of 1 F (or larger) on the BOOT output. Additionally the minimum BOOT capacitance must be larger than two times the capacitor value connected to the MAIN and AUXILIARY LDO outputs (in case LDO AUX is connected to the BOOT output). The TPS6512x peak-current control scheme is inherently stable. The filtering capacitors on VGH and VGL outputs are basically determined as a function of the required current and permissible ripple voltage. For small form-factor TFT-LCD applications, typical values in the range of 100 nF to 1 F are usually required. A good starting point is 220 nF. For high output power on VGH and VGL outputs, the capacitance may need to approach 2 F. For stable operation, TPS6512x requires a 220-nF ceramic capacitor on the MAIN and AUXILIARY LDO outputs. Larger capacitor values can be used to achieve lower output-voltage noise without sacrificing stability. In general, ceramic X5R types are strongly recommended for their low ESR and ESL and capacitance-versus-bias-voltage stability. Be certain that the capacitors used are rated for the maximum voltage with adequate safety margin.
LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design. If the layout is not carefully done, the regulator could become unstable, displaying double or missing pulses as well as EMI problems. Therefore, use wide, short traces for the main current paths. Route these traces first. Place the input capacitor as close as possible to the IC pins as well as the inductor and output capacitors. Place the inductor and diode as close as possible to the switch pins to minimize noise coupling into other circuits. Use a common ground node for power ground and a different one for control ground (AGND) to minimize the effects of ground noise. Connect these ground nodes together (star point) at any place close to one of the ground pins of the IC and make sure that small-signal components returning to the AGND pin do not share the switching-current paths. Feedback pins and divider networks are high-impedance nodes and should therefore be routed away from the inductor and shielded with a ground plane or trace to minimize noise coupling into the control loop.
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APPLICATION EXAMPLES
TPS65120 VIN 2.7 V to 5.5 V GPIO GATE VGH up to +20 V/2 mA C2 220 nF R2 LDOIN LDOOUT AGND
A
D1 SWN L1 10H SWP FBL R3 R4 VGL down to -18 V/2 mA C3 220 nF
VIN C1 2.2 F RUN EN
VGH R1 FBH
VMAIN FBM BOOT
R5 C4 R6 1F
VMAIN 3.0 V to 5.3 V/25 mA C5 220 nF
VLOGIC = 3.3 V C6 220 nF
A
PGND
Figure 23. Complete TFT-LCD Power Supply from 1 cell Li-Ion
TPS65123 VIN 2.7 V to 5.5 V VIN C1 RUN EN RUN GATE VGH R1 C2 220 nF R2 VMAIN FBM BOOT PGND
A
D1 SWN L1 SWP FBL R4b RUN N-MOS VISHAY SI1032 R3 C3 220 nF VGL
VGH
FBH R4a
VMAIN R5 C4 1 F R6 C5 220 nF
AGND
A
VGL = VMAIN x
R3 R 4a
1.2 - VMAIN R 4b = R3 - R 4a VGL _ OFFThreshold - 1.2
VMAIN = 5.0 V, VGH = 15 V, VGL = -10 V R3 = 540 k, R4a = 270 k, R4b = 680 k
Figure 24. VGL VMAIN Power Down-Sequencing Threshold Shifting
EN
Negative LDO
VGL2 C7
TPS65121 VIN C1 RUN EN GPIO GATE VGH VGH R1 C2 220 nF R2 LDOIN LDOOUT AGND
A
D1 SWN L1 R4 SWP FBL R3 C3 > C7 VGL1
VIN
FBH
VMAIN FBM BOOT
R5 C4 R6 1 F C5 220 nF
VMAIN
VLOGIC C6 220 nF
A
PGND
Negative LDO = TPS723xx series
Figure 25. Additonal Negative Gate Driver Voltage
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TPS65120
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TPS65124 VIN C1 2.2 F VIN RUN GATE EN VGH C6 C2 220 nF 10 pF R2 GPIO2 GPIO3 R1 FBH VMAIN FBM BOOT SWP FBL SWN L1
D1 VGL R3 C7 10 pF R4 C3 220 nF
GPIO1 VGH
VMAIN R5 C4 4.7 F R6 C5 2.2 F N&P MOS C8 100 nF
ENVGH ENVGL AGND
A
PGND
A
GPIO4
N&P MOS = VISHAY Si1016 D1 = VISHAY BAT54A-HT3
Figure 26. Fully Programmable Sequencing Featuring Very Low Gate Ripple Voltage
TPS65124 VIN C1 RUN GATE EN VPOS 12 V C2 220 nF R2 VGH R1 FBH VMAIN FBM BOOT ENVGH ENVGL R1 R2 R3 R5 R6 = 887 k = 100 k = R4 = 680 k = 845 k = 270 k AGND
A
D1 SWN L1 SWP FBL R3 R4 C3 220 nF VNEG
-12 V
VIN
ENVGH, ENVGL (2V/div) VGH (5V/div)
VGH
VPOS VREF R5 C4 1 F R6 PGND
A
EN
C5 220 nF
VGL (5V/div)
VIN = 3.6V EN = RUN = HIGH RGH = 60 k RGL = 60 k
VGL
Figure 27. Dual Output Tracking Regulator with High Accuracy Reference Voltage
TPS65123 VIN C1 RUN EN RUN GATE VGH R1 C2 FBH R2 VMAIN FBM AGND
A
D1 SWN L1 SWP FBL
EN TPS65120 LDO
EN IN
VIN
VGL R3 C3
VGH BOOT C4 2.2 F
OUT
R4
VMAIN R5 C5 1uF R6
A
PGND
External LDO = TPS792xx series Ext. LDO nominal output voltage setting recommended at 1% lower than VMAIN.
Figure 28. Boosting Main Output Current, IMAIN > 25mA
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